Fault Tolerance TSV Planning for Three Dimensional Integrated Circuits
- Speaker：Qi Xu
- Time：2018-12-04（Tues.）10:00-11:00
- Location：Conference room 1008, IPARK A7 Building
Address：Office 444A, South Tower, CoE Building,SUSTech,1088 Xueyuan Avenue, Nanshan District, Shenzhen 518055, P.R. China